As power devices, trench-type MOS power devices, each having a bilayer gate in a trench, provide the advantages of a higher breakdown voltage, a lower on resistance and a faster switching speed. Normally, a first layer of polysilicon is grounded, and a second layer of polysilicon is used as a gate conductor. An oxide layer is arranged between the two layers of polysilicon, and has a thickness which is well controlled for preventing leakage current and a low breakdown voltage.
Referring to FIGS. 1 and 2, in a conventional process for forming a trench-type MOS power device, a trench is firstly formed in a substrate 10. An oxide layer 20 is then formed in the trench and on a surface of the substrate 10. A first layer 30 of polysilicon is then formed in the trench and on the surface of the substrate 10. The first layer 30 of polysilicon is then etched to remove the portion of the first layer 30 of polysilicon that is on the surface of the substrate 10. Meanwhile, the portion of the first layer 30 of polysilicon in the trench is etched to a predetermined depth below the surface of the substrate 10.
However, in a case that the trench has a large depth, there is usually a recess 31 in the first layer 30 of polysilicon above the trench when the first layer 30 of polysilicon is formed in the trench and on the surface of the substrate 10, as shown in FIG. 1. The recess 31 remains in the portion of the first layer 30 of polysilicon in the trench after the first layer 30 of polysilicon is etched, as show in FIG. 2. After the oxide layer is formed, portions of the oxide layer near corners of the first layer 30 of polysilicon have poor quality and a thickness that is not well controlled. Consequently, the power device will have leakage current and a low breakdown voltage.
In a conventional process, the first layer 30 of polysilicon may be planarized by chemical mechanical polishing (CMP) to remove the recess 31, followed by etching. However, it makes the process complex and leads to increased cost.